EPF8636AQC160-3N

Product Summary

The EPF8636AQC160-3N is a Programmable Logic Device. It combines the benefits of both erasable programmable logic devices (EPLDs) and field-programmable gate arrays (FPGAs). The EPF8636AQC160-3N is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. The EPF8636AQC160-3N provides a large number of storage elements for applications such as digital signal processing (DSP), wide-data-path manipulation, and data transformation.

Parametrics

EPF8636AQC160-3N absolute maximum ratings: (1)Supply voltage:-2.0V to 7.0V; (2)DC input voltage:-2.0V to 7.0V; (3)DC output current, per pin:-25mA to 25mA; (4)Storage temperature:-65℃ to 150℃; (5)Ambient temperature:-65℃ to 135℃; (6)Junction temperature:135℃.

Features

EPF8636AQC160-3N features: (1)In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller; (2)Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation; (3)Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices; (4)MultiVoltTM I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels Low power consumption (typical specification is 0.5 mA or less in standby mode); (5)Peripheral register for fast setup and clock-to-output delay; (6)Fabricated on an advanced SRAM process; (7)Available in a variety of packages with 84 to 304 pins; (8)Powerful I/O pins; (9)Programmable output slew-rate control reduces switching noise; (10)FastTrack Interconnect continuous routing structure for fast, predictable interconnect delays; (11)Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions); (12)Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions); (13)Tri-state emulation that implements internal tri-state nets.

Diagrams