LPC2365FBD100

Product Summary

The LPC2365FBD100 is a single-chip 16-bit microcontroller. It combines the microcontroller with up to 512 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. The LPC2365FBD100 is ideal for multi-purpose serial communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), four UARTs, an SPI interface, two Synchronous Serial Ports (SSP), three I2C interfaces, and an I2S interface. The applications of the LPC2365FBD100 include: Industrial control, Medical systems, Protocol converter, Communications.

Parametrics

LPC2365FBD100 absolute maximum ratings: (1)VDD(3V3) supply voltage (3.3 V): 3.0 to 3.6 V; (2)VDD(DCDC)(3V3) DC-to-DC converter supply voltage(3.3 V): 3.0 to 3.6 V; (3)VDDA analog 3.3 V pad supply voltage: -0.5 to +4.6 V; (4)Vi(VBAT) input voltage on pin VBAT: -0.5 to +4.6 V; (5)Vi(VREF) input voltage on pin VREF: -0.5 to +4.6 V; (6)VIA analog input voltage: -0.5 to +5.1 V; (7)VI input voltage: -0.5 to +6.0 V; (8)IDD supply current: 100 mA; (9)ISS ground current: 100 mA; (10)Tstg storage temperature: -65 to +150 ℃; (11)Ptot(pack) total power dissipation (per package): 1.5 W; (12)VESD electrostatic discharge voltage: -2500 to +2500 V.

Features

LPC2365FBD100 features: (1)ARM7TDMI-S processor, running at up to 72 MHz; (2)Up to 512 kB on-chip flash program memory with In System Programming (ISP) and In-Application Programming (IAP)capabilities. Flash program memory is on the ARM local bus for high performance CPU access; (3)8 kB/32 kB of SRAM on the ARM local bus for high performance CPU access; (4)16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM; (5)8 kB SRAM for general purpose DMA use also accessible by the USB; (6)Dual Advanced High-performance Bus (AHB) system that provides for simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem.

Diagrams