(China (Mainland))
Product Summary
The MX29F002NTQC-70G is a 2-mega bit Flash memory organized as 256K bytes of 8 bits only. The MX29F002NTQC-70G is packaged in 32-pin PDIP,PLCC and 32-pin TSOP(I). It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers. The standard MX29F002NTQC-70G offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states.
Parametrics
MX29F002NTQC-70G absolute maximum ratings: (1)Ambient Operating Temperature:0℃ to 70℃; (2)Storage Temperature:-65℃ to 125℃; (3)Applied Input Voltage:-0.5V to 7.0V; (4)Applied Output Voltage:-0.5V to 7.0V; (5)VCC to Ground Potential:-0.5V to 7.0V; (6)A9:-0.5V to 13.5V.
Features
MX29F002NTQC-70G features: (1)262,144x 8 only; (2)Fast access time: 55/70/90/120ns; (3)Low power consumption: 30mA maximum active current(5MHz), 1uA typical standby current; (4)Programming and erasing voltage 5V ± 10%; (5)Command register architecture; (6)Automatically erase any combination of sectors or the whole chip with Erase Suspend capability; (7)Automatically programs and verifies data at specified address; (8)Erase Suspend/Erase Resume: Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation; (9)Status Reply; (10)Data polling & Toggle bit for detection of program and erase cycle completion; (11)Hardware method to disable any combination of sectors from program or erase operations; (12)Sector protect/unprotect for 5V only system or 5V/12V system; (13)100,000 minimum erase/program cycles; (14)Latch-up protected to 100mA from -1 to VCC+1V; (15)Boot Code Sector Architecture; (16)Hardware RESET pin(only for 29F002T/B): Resets internal state machine to read mode; (17)Low VCC write inhibit is equal to or less than 3.2V.
Diagrams
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 MX29F001B |
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Negotiable |
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MX29F001T |
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Negotiable |
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MX29F001T/B |
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Negotiable |
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MX29F002 |
Other |
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Negotiable |
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MX29F002N |
Other |
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Negotiable |
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MX29F002TTI-12 |
Other |
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Negotiable |
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